1. Field of the Invention
The present invention relates to a semiconductor device having a MIM (Metal Insulator Metal) capacitor element suitable for an analog circuit and a method of manufacturing the same.
2. Description of the Prior Art
C-MOS type semiconductor devices (integrated circuit), in which a capacitor element used for an analog circuit is formed on a semiconductor substrate, have been developed. Among these semiconductor devices, each of which has a S/H (Sample/Hold) circuit connected to a D/A (digital/analog) converter and an A/D (analog/digital) converter, are required to retain charges in the capacitor element precisely.
FIG. 1 is a circuit diagram showing an example of the S/H circuit. The S/H circuit comprises a switching element 2, a capacitor element 3 and a buffer circuit 4. In addition, an input terminal 1 receives an analog signal, and an A/D converter (not shown) is connected to an output terminal 5.
The switching element 2 receives a clock signal, and the switching element 2 is rendered to be ON when the clock signal is high (H) in level, thus charging the capacitor element 3 with charges in accordance with a voltage of the analog signal. When the clock signal becomes low (L) in level, the switching element 2 is rendered to be OFF. Thus, the capacitor element 3 retains the charges charged therein. The buffer circuit 4 supplies to the A/D converter the voltage in accordance with the charges charged in the capacitor element 3. Thus, a digital signal in accordance with the voltage of the analog signal is output from the A/D converter.
As the capacitor element formed in the C-MOS type semiconductor device, enumerated are (1) one having the same structure as that of a MOS transistor, that is, one constituting a capacitor by a polysilicon gate and a semiconductor substrate, (2) one constituted by a pair of polysilicon films laminated on a semiconductor substrate so as to sandwich an insulating film therebetween, which is so-called a double polysilicon capacitor element, and (3) one constituted by a pair of metallic films laminated on a semiconductor substrate so as to sandwich an insulating film therebetween, which is so-called a MIM capacitor element.
Incidentally, since polysilicon offers a relatively high resistivity, use of the polysilicon for one or both of electrodes of the capacitor elements means that a resistor element is in series connected to the capacitor element. Accordingly, the capacitor element using the polysilicon is not suitable for the S/H circuit which is required to operate at a high speed. Moreover, since the polysilicon is a semiconductor, the capacitor element using the polysilicon has also a drawback that a thickness of a depletion layer changes in response to a voltage applied between the electrodes, leading to a change of a capacitance value thereof.
Contrary to this, the MIM capacitor element has an advantage that both of electrodes thereof are made of a metallic film and show low resistivity and a capacitance value does not change by a voltage applied.
FIG. 2 is a section view showing an example of a conventional semiconductor device comprising the MIM capacitor element.
Element isolation regions 11 which partition a semiconductor substrate 10 into a plurality of element regions are provided on the semiconductor substrate 10. In each of the element regions partitioned by the element isolation region 11, a pair of impurity diffusion regions 12 that are source/drain of the MOS transistor are formed in a state where they are separated from each other. A gate 13 is formed above a region between the pair of impurity diffusion regions 12 so as to interpose an insulating film (gate insulating film) therebetween.
Four wiring layers are provided above the semiconductor substrate 10. Herein, the four wiring layers indicate a first wiring layer (lowermost layer) 15, a second wiring layer 17, a third wiring layer 19 and a fourth wiring layer (uppermost layer) 23, respectively, in the order of closeness to the semiconductor substrate 10. Interlayer insulating films 25a, 25b, 25c and 25d are formed between the semiconductor substrate 10 and the first wiring layer 15, the first wiring layer 15 and the second wiring layer 17, the second wiring layer 17 and the third wiring layer 19, and the third wiring layer 19 and the fourth wiring layer 23, respectively. A predetermined pattern wiring is formed in each of the wiring layers 15, 17, 19 and 23 respectively.
In the example shown in FIG. 2, one of the impurity diffusion regions 12 of the MOS transistor is connected to a wiring 15a of the first wiring layer 15 via a via 14a, and the gate 13 is connected to a wiring 15b of the first wiring layer 15 via a via 14b. Furthermore, the wiring 15a is connected to a wiring 17a of the second wiring layer 17 via a via 16a, and the wiring 15b is connected to a wiring 17b of the second wiring layer 17 via a via 16b. Still furthermore, the wiring 17a is via a via 18a connected to a lower electrode 19a of a capacitor element 24 formed in the third wiring layer 19, and the wiring 17b is connected to the wiring 19b of the third wiring layer 19 via a via 18b. 
A capacitance insulating film 20 is formed on the lower electrode 19a, and an upper electrode 21 is formed on the capacitance insulating film 20.
In the fourth wiring layer 23, formed are a shield 23a covering the upper portion of the capacitor element 24 and a lead wiring 23b connected to the upper electrode 21 and the wiring 19b respectively via the vias 22a and 22b. 
A passivation film (not shown) made of polyimide or the like is formed on the fourth wiring layer 23. The semiconductor substrate 10 in which these wiring layers 15, 17, 19 and 23 and the passivation film are formed is sealed in a package (not shown) made of resin or the like.
Although the lower electrode of the MIM capacitor element is usually formed simultaneously with formation of the wiring in the wiring layer, the capacitor insulating film and the upper electrode must be formed independently from the wiring layer and the interlayer insulating film. Accordingly, if the lower electrode of the MIM capacitor element is formed by use of the wiring layer, for example, the first wiring layer, which is close to the semiconductor substrate, a large step difference (unevenness) is produced between a formation region of the MIM capacitor element and a region around the formation region, and it is difficult to form a minute wiring above the MIM capacitor element.
Therefore, as described above, the lower electrode of the MIM capacitor element is formed in the wiring layer immediately under the uppermost layer, and the shield covering above the MIM capacitor element is formed in the uppermost layer. In this case, though it becomes difficult to form a micro pattern in the uppermost layer, a demand for the micro pattern in the uppermost layer is generally not strict, and hence it is allowed in many cases.
The inventors of this application consider that the foregoing conventional semiconductor device has the problems described below. Specifically, though the shield 23a is formed above the MIM capacitor element in the foregoing conventional semiconductor device, the lead wiring 23b connecting the upper electrode 21 and the MOS transistor (gate 13) electrically is formed in the fourth wiring layer (uppermost layer) 23. Accordingly, parasitic capacitance is generated between the upper electrode 21 and a conductor outside the package. Then, when the package is being touched or when a radiator is being attached thereto, the value of the parasitic capacitance increases.
For example, when the capacitance insulating film is 50 nm thick, the package is made of plastic and is 0.5 mm thick, the dielectric constant of the capacitance insulating film and the plastic of the package is equivalent, there is no shield on top of the capacitor element, and a conductor of a radiator or the like is placed on the package, then the size of the parasitic capacitance becomes about 1/10000 compared to the value of the MIM capacitor element. This indicates a possibility that about 1/10000 of an external signal of the package is being induced as noises to the signal wiring. If the amplitude of the external signal of the package is equivalent to the amplitude of an internal signal, then the accuracy of the circuit deteriorates to about 13 bit (213=8192).
Signals in a digital audio of a CD (compact disk), etc. are being processed at a accuracy of 16 bits or more at present. Hence, a capacitor element having the above-mentioned accuracy (an accuracy in which parasitic capacitance becomes about 1/10000 to the capacity of the original MIM capacitor element) is insufficient, and therefore a capacitor element having higher accuracy is in demand.